In a display device using such a self-luminous light emitting element as OLED (Organic Light Emitting Diode), organic EL element and EL (Electro Luminescence) element, a passive matrix method and an active matrix method are known as its driving method. The former has a simple structure, but has a problem such that a realization of a large and high luminance display is difficult. Therefore, the active matrix method is developed in recent years in which a current flowing to the light emitting element is controlled by a thin film transistor (TFT) provided in a pixel circuit.
In the case of a display device of the active matrix method, there is a problem that a current flowing to a light emitting element varies due to a variation in current characteristics of driving TFTs, which varies a luminance.
That is, in the case of a display device of the active matrix method, a driving TFT which drives a current flowing to the light emitting element is used in a pixel circuit. When characteristics of these driving TFTs vary, a current flowing to the light emitting element varies, which varies a luminance. Then, various circuits are suggested in which a current flowing to a light emitting element does not vary even when characteristics of driving TFTs in a pixel circuit vary to suppress a variation in luminance. (For example, refer to Patent Documents 1 to 4)
Patent Documents 1 to 3 disclose circuit configurations for preventing variations of current value to be supplied to a light emitting element due to variations in characteristics of driving TFTs provided in pixel circuits. This configuration is referred to as a current write type pixel or a current input type pixel. Patent Document 4 discloses a circuit configuration for suppressing variations of a signal current due to variations of TFTs in a source driver circuit.
FIG. 6 shows a first configuration example of a conventional active matrix display device disclosed in Patent Document 1. The pixel shown in FIG. 6 comprises a source signal line 601, first to third gate signal lines 602 to 604, a current supply line 605, TFTs 606 to 609, a capacitor 610, an EL element 611, and a current source 612 for inputting a video signal.
An operation from a write of a signal current to a light emission is described with reference to FIGS. 7A to 7E. Reference numerals denoting each portion in the drawings correspond to those in FIG. 6. FIGS. 7A to 7C each schematically shows a current flow. FIG. 7D shows a relationship of a current flowing through each path when writing a signal current. FIG. 7E shows a voltage accumulated in the capacitor 610 when writing a signal current, that is a gate-source voltage of the TFT 608.
First, a pulse is inputted to the first gate signal line 602 and the second gate signal line 603 and the TFTs 606 and 607 are turned ON. At this time, a current flowing through the source signal line, that is a signal current is denoted as Idata.
As the current Idata flows through the source signal line, the current path is divided into I1 and I2 in a pixel as shown in FIG. 7A. These relationships are shown in FIG. 7D. It is needless to say that Idata=I1+I2 is satisfied.
A charge is not held in the capacitor 610 at the moment the TFT 606 is turned ON, therefore, the TFT 608 is OFF. Therefore, I2=0 and Idata=I1 are satisfied. In other words, current only flows into the capacitor 610 to be accumulated in the meantime.
After that, as the charge is gradually accumulated in the capacitor 610, a potential difference starts to generate between both electrodes (FIG. 7E). When the potential difference between the both electrodes reaches Vth (a point A in FIG. 7E), the TFT 608 is turned ON and I2 generates. As described above, as Idata=I1+I2 is satisfied, current still flows and a charge is further accumulated in the capacitor while I1 decreases gradually.
The charge keeps being accumulated in the capacitor 610 until the potential difference between the both electrodes, that is a gate-source voltage of the TFT 608 reaches a desired voltage, that is a voltage (VGS) which can make the TFT 608 flow the current Idata. When the charge stops being accumulated (a point B in FIG. 7E), the current I2 stops flowing and the TFT 608 flows a current corresponding to VGS at that time and Idata=I1 is satisfied (FIG. 7B). In this manner, a steady state is obtained. Thus, a write operation of a signal is terminated. At last, selections of the first gate signal line 602 and the second gate signal line 603 are terminated to turn OFF the TFTs 606 and 607.
An operation to set to supply a predetermined current in this manner is referred to as a set operation.
Subsequently, a light emitting operation starts. A pulse is inputted to the third gate signal line 604 to turn ON the TFT 609. As the capacitor 610 holds VGS which is written before, the TFT 608 is ON and the current Idata flows from the current supply line 605. Thus, the EL element 611 emits light. Provided that the TFT 608 is set to operate in a saturation region, Idata keeps flowing without changing even when a source-drain voltage of the TFT 608 changes.
An operation to output a set current in this manner is hereinafter referred to as an output operation. As a merit of the current write type pixel of which example is shown above, a desired current can be accurately supplied to an EL element because a gate-source voltage required to flow the current Idata is held in the capacitor 610 even when the TFTs 608 have variations in characteristics and the like. Therefore, a luminance variation due to the variations in characteristics of TFTs can be suppressed.
The aforementioned examples relate to a technology for compensating a change of current due to variations of driving TFTs in pixel circuits, however, the same problem occurs in a source driver circuit as well. Patent Document 4 discloses a circuit configuration for preventing a change of a signal current due to variations of the TFTs in the source driver circuit generated in fabrication.    [Patent Document 1]    Published Japanese Translation of PCT International Publication for Patent Application No. 2002-517806    [Patent Document 2]    International Publication WO01/06484    [Patent Document 3]    Published Japanese Translation of PCT International Publication for Patent Application No. 2002-514320    [Patent Document 4]    International Publication WO02/39420    [Patent Document 5]    Published Japanese Translation of PCT International Publication for Patent Application No. 2003-66908